{"title":"两种不同技术实现的sram覆盖开口iddt测试效率的比较","authors":"G. Gyepes, J. Brenkus, D. Arbet, V. Stopjaková","doi":"10.1109/DDECS.2011.5783118","DOIUrl":null,"url":null,"abstract":"The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 µm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies\",\"authors\":\"G. Gyepes, J. Brenkus, D. Arbet, V. Stopjaková\",\"doi\":\"10.1109/DDECS.2011.5783118\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 µm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.\",\"PeriodicalId\":231389,\"journal\":{\"name\":\"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems\",\"volume\":\"84 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2011.5783118\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2011.5783118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies
The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 µm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.
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