D. Tuckerman, L.-O. Bauer, N. Brathwaite, J. Demmin, K. Flatow, R. Hsu, P. Kim, C.-M. Lin, K. Lin, S. Nguyen, V. Thipphavong
{"title":"层压存储器:一种新的mcm三维封装技术","authors":"D. Tuckerman, L.-O. Bauer, N. Brathwaite, J. Demmin, K. Flatow, R. Hsu, P. Kim, C.-M. Lin, K. Lin, S. Nguyen, V. Thipphavong","doi":"10.1109/MCMC.1994.292526","DOIUrl":null,"url":null,"abstract":"A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate (\"MCM-D\"), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Laminated memory: a new 3-dimensional packaging technology for MCMs\",\"authors\":\"D. Tuckerman, L.-O. Bauer, N. Brathwaite, J. Demmin, K. Flatow, R. Hsu, P. Kim, C.-M. Lin, K. Lin, S. Nguyen, V. Thipphavong\",\"doi\":\"10.1109/MCMC.1994.292526\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate (\\\"MCM-D\\\"), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests.<<ETX>>\",\"PeriodicalId\":292463,\"journal\":{\"name\":\"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1994.292526\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1994.292526","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Laminated memory: a new 3-dimensional packaging technology for MCMs
A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate ("MCM-D"), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests.<>