一种用于64mb dram的1.5 V电路技术

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111076

Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh

{"title":"一种用于64mb dram的1.5 V电路技术","authors":"Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh","doi":"10.1109/VLSIC.1990.111076","DOIUrl":null,"url":null,"abstract":"A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"A 1.5 V circuit technology for 64 Mb DRAMs\",\"authors\":\"Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh\",\"doi\":\"10.1109/VLSIC.1990.111076\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future\",\"PeriodicalId\":239990,\"journal\":{\"name\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1990.111076\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 32

摘要

描述了一种用于1.5 v, 64mb dram的低压电路技术，旨在实现从现有趋势预测的合理速度性能。该DRAM采用新颖的低压电路设计。获得了50 ns的RAS接入时间，功耗低至44 mW。这些结果表明，低压电池驱动的DRAM是未来有希望的目标

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 1.5 V circuit technology for 64 Mb DRAMs

A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

自引率

0.00%

发文量