BiCMOS亚微米编译存储器

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186106

J. Drummond, M. Lepkowski

{"title":"BiCMOS亚微米编译存储器","authors":"J. Drummond, M. Lepkowski","doi":"10.1109/ASIC.1990.186106","DOIUrl":null,"url":null,"abstract":"An advanced submicron BiCMOS process and an ASIC memory compiler are discussed. The BICMOS process uses bipolar transistors to enhance the fast CMOS transistors by driving heavily loaded nodes at high speeds. The multiple layers of metal in the process significantly increase the gate density available for system-level design.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"BiCMOS submicron compiler memories\",\"authors\":\"J. Drummond, M. Lepkowski\",\"doi\":\"10.1109/ASIC.1990.186106\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An advanced submicron BiCMOS process and an ASIC memory compiler are discussed. The BICMOS process uses bipolar transistors to enhance the fast CMOS transistors by driving heavily loaded nodes at high speeds. The multiple layers of metal in the process significantly increase the gate density available for system-level design.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186106\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

讨论了一种先进的亚微米BiCMOS工艺和一种ASIC存储器编译器。BICMOS工艺使用双极晶体管，通过高速驱动重载节点来增强快速CMOS晶体管。该工艺中的多层金属显著增加了系统级设计的栅极密度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

BiCMOS submicron compiler memories

An advanced submicron BiCMOS process and an ASIC memory compiler are discussed. The BICMOS process uses bipolar transistors to enhance the fast CMOS transistors by driving heavily loaded nodes at high speeds. The multiple layers of metal in the process significantly increase the gate density available for system-level design.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

自引率

0.00%

发文量

期刊最新文献

A development system for an SRAM-based user-reprogrammable gate array Automated CAE tools for full custom design of bipolar analog ASICs A 200 MHz 100 K ECL output buffer for CMOS ASICs Multi circular buffer controller chip for advanced ESM system Rapid prototyping, is there an educational dilemma? (ASIC design)