一个1.2V 84dB 8mW时间交错采样和保持电路在90 nm CMOS

2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI:10.1109/EDSSC.2013.6628204

A. Zjajo

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引用次数: 0

摘要

本文报道了一种基于闭环开关电容技术的时间交错采样保持电路的设计、效率和测量结果。在120 MS/s下具有84 dB动态范围的原型样品和保持器是在标准的单聚，六金属90 nm CMOS上制造的，在1.2 V电源下仅消耗8 mW，尺寸为0.22 mm2。

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A 1.2V 84dB 8mW time-interleaved sample and hold circuit in 90 nm CMOS

This paper reports design, efficiency and measurement results of time interleaved sample and hold circuit based on closed loop switched capacitor technique. The prototype sample and hold with 84 dB dynamic range at 120 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 8 mW at 1.2 V power supply and measures 0.22 mm2.

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2013 IEEE International Conference of Electron Devices and Solid-state Circuits

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