A 5.5/spl mu/m CMOS Image Sensor Cell Utilizing A Buried Reset Channel

A CMOS image sensor cell suitable for miniaturization is proposed. The number of gate polysilicons in a cell was reduced from 3 to 1 by utilizing a stacked capacitor and a buried reset channel. A cell of 5.5x5.5ym2 applicable to 1/4 inch VGA device was produced with 23% of photodiode area using 0.7pm design rule. Fabrication processes are compatible with stacked capacitor DRAM. Saturation signal amplitude of 1.OV and conversion gain of 9uVlelectron were obtained with 5V power Introduction The CMOS image sensor has advantages of low driving voltage and low consumption electric power compared with the CCD image sensor. It also has the possibility of integrating driving circuitry and adding functionality on the same chip[l]. The problem of fixed pattem nose, which previously had prevented utilization of the CMOS image sensor, was resolved by integrating noise canceling circuits[2]. Consequently, the CMOS image sensor has become the focus of mounting interest in recent years. The important problem which still remains is the difficulty of manufacturing a small cell array since each cell contains three transistors for address, reset and amplify other than a photodiode. In particular, the arrangement of 3 gate polysilicons restricts the cell size. In this paper, we report a miniaturized cell which contains only 1 gate and has a simple layout. Circuit The cell circuit composition is shown in Fig.1 where the conventional transistor address cell is also shown for purposes of comparison. Photodiode (PD) converts photons into electrons, which lowers detection node (DN) voltage. Then gate voltage of the amplification transistor (Amp) is modulated, and a signal is read out to the signal line (Sig) by the source follower which consists of the load transistor (Load) fabricated in the upper part of cell array. Whereas a conventional cell has an address transistor (Ad) for selecting a row, the proposed cell has a stacked capacitor (Ad) which controls the detection node potential. Whereas a conventional cell has a reset transistor (R) for discharging photoelectrons, the proposed cell has a buried reset channel (R) without a gate polysilicon. Structure and Operation Shown in Fig.2 are the structure and potential diagrams along with the cross section from detection node to drain. Drain and detection node are formed by the conventional n-type diffusion layer, while reset channel is formed by thin n-type ionimplantation which sets channel depletion voltage (Vr) higher than OV and lower than drain voltage (Vdd). The cell is operated by 3-level driving pulse[3]. During the integration period, address line keeps a middle level (‘M’) and detection node holds photoelectrons (Signal). Photoelectrons can be contained until detection node potential becomes equal to Vr. Photoelectrons beyond it are discharged to drain through the reset channel. When the address line is first set to a high voltage (‘H’) so that detection node potential is made higher than that in other rows, signal level of the selected row is read out to the signal line. Next, address line is set to low voltage (‘L’), and then detection node potential falls and photoelectrons are discharged supply. to drain until detection node potential becomes equal to Vr. Next, address line is set to ‘H’ again, then 0 level of the cell is read out to the signal line. Finally, address line is returned to ‘M’ and photoelectrons are stored till the next reset time. Layout Fig3 compares the layouts of the proposed cell and the conventional transistor address cell. Only active regions, gates and contacts are represented here for simplicity. Although the form of a cell goes in and out with adjacent cells, their arrangement serves as the right square lattice. It can be easily seen in the conventional cell that the cell size is determined by arrangement of 3 gate polysilicons. In the proposed cell, a gate is used only in the amplification transistor so that the pattem is simpler. It can be seen that the cell area is about half of the conventional one even with a larger photodiode area. A cell is easily completed by forming a stacked capacitor, signal line and drain wiring above them. We fabricated a cell of 5.5x5.5ym2, applicable to 1/4 inch VGA device, by the 0.7ym design rule. The process is compatible with stacked DRAM forming capacitors between second and third polysilicons. Signal line and drain wiring are made by fmt and second aluminum, respectively. Photodiode occupies 23% of the cell area. Results and Discussion The cell was driven by drain voltage of 5V, address line voltage of 0-2.5-5V and source follower current of 10uA. Voltage transition on the signal line is shown in Fig.4. At the dark time, a signal level and zero level have the same voltage. When light is incident, the signal level falls according to the light intensity. The voltage after reset does not change with the dark time. When light intensity is further increased, signal level saturates. The saturation signal amplitude is 1 .OV. The observed value of Vr was 3.3V. Detection node potential was raised to 5.2V at the time of 0 level read-out. Thus, the detection node potential can exceed Vdd in this type of cell so that operating point of the source follower can be larger than in the conventional cell whose detection node potential is determined by subtracting threshold voltage of reset transistor from Vdd. On the other hand the proposed cell is at a disadvantage in conversion gain, since address capacitance is added to detection node capacitance. However the conversion gain of the proposed cell was found to be 9pV/electron at signal line. This value is comparable to that of CCD sensor. The summary of the characteristics of the cell is presented in Table 1, Conclusion A 5.5ym cell for CMOS image sensor which is applicable to 1/4 inch VGA device was fabricated by the 0.7pm design rule while maintaining photodiode area, by introducing a stacked capacitor and a buried reset channel for address and reset element. Fabrication process is compatible with stacked capacitor DRAM. The operation was verified and signal saturation amplitude 1 .OV was obtained by 5V supply voltage. References [ I1E.R. Fossum, IEDM. Tech. Dig., pp. 17, 1995 [2]R.H. Nixon, etal.,Proc. SPE-lnt. Soc. Opt. Eng. vo1.2415, pp,I17,1995 [3]J. Nakamura, et al., IEEETrans. ED. Vo1.42, No.9, pp.1693, 1995 75 4-93081 3-75-1 197 1997 Symposium on VLSl Technology Digest of Technical Papers