一种集成7T2R非易失SRAM的rram,用于正常关闭计算应用

S. Sheu, Chia-Chen Kuo, Meng-Fan Chang, P. Tseng, L. Chih-Sheng, Min-Chuan Wang, Chih-He Lin, Wen-Pin Lin, Tsai-Kan Chien, Sih-Han Lee, Szu-Chieh Liu, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Ching-Chih Hsu, Frederick T. Chen, K. Su, T. Ku, M. Tsai, M. Kao
{"title":"一种集成7T2R非易失SRAM的rram,用于正常关闭计算应用","authors":"S. Sheu, Chia-Chen Kuo, Meng-Fan Chang, P. Tseng, L. Chih-Sheng, Min-Chuan Wang, Chih-He Lin, Wen-Pin Lin, Tsai-Kan Chien, Sih-Han Lee, Szu-Chieh Liu, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Ching-Chih Hsu, Frederick T. Chen, K. Su, T. Ku, M. Tsai, M. Kao","doi":"10.1109/ASSCC.2013.6691028","DOIUrl":null,"url":null,"abstract":"This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application\",\"authors\":\"S. Sheu, Chia-Chen Kuo, Meng-Fan Chang, P. Tseng, L. Chih-Sheng, Min-Chuan Wang, Chih-He Lin, Wen-Pin Lin, Tsai-Kan Chien, Sih-Han Lee, Szu-Chieh Liu, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Ching-Chih Hsu, Frederick T. Chen, K. Su, T. Ku, M. Tsai, M. Kao\",\"doi\":\"10.1109/ASSCC.2013.6691028\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"2007 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6691028\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691028","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 36

摘要

本研究展示了一种具有3D ReRAM堆叠结构的新型7T2R非易失性SRAM (nvSRAM),用于正常关闭计算应用。这种结构使SRAM在有源模式下能充分发挥其性能,在断电模式下能减小漏电流。基于HfOx的高性能ReRAM用于高速存储元件,具有瞬时开启特性。目前的7T2R nvSRAM单元包括一个1T2R RRAM(1晶体管/2电阻存储器)单元和一个6T SRAM电路,该电路具有低面积损耗和实现nvSRAM功能。与6T SRAM和6T2R nvSRAM相比,写空间分别提高了1.03倍和1.37倍。7T2R结构的访问时间和读写功耗优于8T2R结构。最后,用0.18 μm TSMC FEOL和ITRI BEOL制备了16 Kb的宏。根据测量结果,VDDmin可低至0.7 V,访问时间可快至8.3 ns,无焊盘延迟。在ReRAM单元中,SET和RESET的数据存储时间仅为10 ns。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application
This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Future mobile society beyond Moore's Law A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS Collaborative innovation for future mobile applications A 0.5V 34.4uW 14.28kfps 105dB smart image sensor with array-level analog signal processing An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1