{"title":"VLSI电路与系统的容错设计","authors":"P.V.C.V. Reddy","doi":"10.1109/ASIC.1990.186075","DOIUrl":null,"url":null,"abstract":"The ever-increasing complexity of very large scale integration (VLSI) has a considerable impact on the design and implementation of fault-tolerant circuits and systems. The techniques of fault-tolerance are well established. VLSI, however, introduces problems in fault-tolerant design. An overview of the design and implementation of fault-tolerant systems in a VLSI environment is presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fault-tolerant design of VLSI circuits and systems\",\"authors\":\"P.V.C.V. Reddy\",\"doi\":\"10.1109/ASIC.1990.186075\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ever-increasing complexity of very large scale integration (VLSI) has a considerable impact on the design and implementation of fault-tolerant circuits and systems. The techniques of fault-tolerance are well established. VLSI, however, introduces problems in fault-tolerant design. An overview of the design and implementation of fault-tolerant systems in a VLSI environment is presented.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186075\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fault-tolerant design of VLSI circuits and systems
The ever-increasing complexity of very large scale integration (VLSI) has a considerable impact on the design and implementation of fault-tolerant circuits and systems. The techniques of fault-tolerance are well established. VLSI, however, introduces problems in fault-tolerant design. An overview of the design and implementation of fault-tolerant systems in a VLSI environment is presented.<>