An efficient shared-buffer for high speed ATM networks

This paper describes an efficient shared-buffer component suitable for high-speed ATM networks. The component stores incoming ATM cells into individual virtual linked lists, according to the network connection that the cell belongs to. All linked lists are realized utilizing a single memory component, thus achieving maximal memory utilization. Furthermore, using the proposed buffering technique, it is feasible to control and monitor buffered data on a per connection basis, enabling network nodes to perform sophisticated policing and control functions on the incoming data streams. Although the particular component has been designed for ATM networks, the proposed buffering architecture can be efficiently used in other packet networks as well. The shared-buffer component, which has been used in an existing ATM multiplexer, is presented from an implementation point of view and specific ideas concerning the hardware realization are given. Furthermore, additional features that the component can support are presented along with hardware realization. Some possible utilization scenarios, where the component could be efficiently used, are finally presented.