{"title":"超大尺寸GaN hemt栅极工艺模块开发的考虑","authors":"Ragnar Ferrand-Drake del Castillo, N. Rorsman","doi":"10.1109/CSW55288.2022.9930349","DOIUrl":null,"url":null,"abstract":"With the overarching goal of attaining mm-wave GaN High Electron Mobility Transistors (HEMTs), vertical and lateral downscaling is of essence. Utilizing Passivation first technology (coupled with mini-FP T-gates), Schottky Gate (SG) is formed by Fluorine plasma etching, where the plasma etching allows highly defined nanoscale gate-length (Lg) features. However, it damages the crystalline structure of the top barrier layer and leads to Fluorine implantation with ramifications on the sheet carrier density(ns), mobility (μ) and threshold-voltage (VTH) shift towards enhancement mode. In this study, CF4 or NF3 etching with varying over etch times are implemented, with high temperature annealing (600–800°C) post gate recess etching to repair crystal structure damages caused by the etch process.","PeriodicalId":382443,"journal":{"name":"2022 Compound Semiconductor Week (CSW)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Considerations in the development of a gate process module for ultra-scaled GaN HEMTs\",\"authors\":\"Ragnar Ferrand-Drake del Castillo, N. Rorsman\",\"doi\":\"10.1109/CSW55288.2022.9930349\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the overarching goal of attaining mm-wave GaN High Electron Mobility Transistors (HEMTs), vertical and lateral downscaling is of essence. Utilizing Passivation first technology (coupled with mini-FP T-gates), Schottky Gate (SG) is formed by Fluorine plasma etching, where the plasma etching allows highly defined nanoscale gate-length (Lg) features. However, it damages the crystalline structure of the top barrier layer and leads to Fluorine implantation with ramifications on the sheet carrier density(ns), mobility (μ) and threshold-voltage (VTH) shift towards enhancement mode. In this study, CF4 or NF3 etching with varying over etch times are implemented, with high temperature annealing (600–800°C) post gate recess etching to repair crystal structure damages caused by the etch process.\",\"PeriodicalId\":382443,\"journal\":{\"name\":\"2022 Compound Semiconductor Week (CSW)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 Compound Semiconductor Week (CSW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSW55288.2022.9930349\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 Compound Semiconductor Week (CSW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSW55288.2022.9930349","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Considerations in the development of a gate process module for ultra-scaled GaN HEMTs
With the overarching goal of attaining mm-wave GaN High Electron Mobility Transistors (HEMTs), vertical and lateral downscaling is of essence. Utilizing Passivation first technology (coupled with mini-FP T-gates), Schottky Gate (SG) is formed by Fluorine plasma etching, where the plasma etching allows highly defined nanoscale gate-length (Lg) features. However, it damages the crystalline structure of the top barrier layer and leads to Fluorine implantation with ramifications on the sheet carrier density(ns), mobility (μ) and threshold-voltage (VTH) shift towards enhancement mode. In this study, CF4 or NF3 etching with varying over etch times are implemented, with high temperature annealing (600–800°C) post gate recess etching to repair crystal structure damages caused by the etch process.