{"title":"以不连续终止的高速串行I/ o中ISI的建模","authors":"A. Dey, H. Song","doi":"10.1109/EPEPS.2011.6100225","DOIUrl":null,"url":null,"abstract":"Timing jitter remains one of the most important design issues for successful operation of high speed serial links. This abstract introduces methods to model and estimate data dependent jitter (DDJ), in presence of capacitive and inductive discontinuities that result due to vias and right angular bends. The model shows that these discontinuities can have significant impact on DDJ, especially at high data rates. The proposed model is extensively verified with SPICE and show very good results.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Modeling of ISI in high speed serial I/Os terminated with discontinuities\",\"authors\":\"A. Dey, H. Song\",\"doi\":\"10.1109/EPEPS.2011.6100225\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Timing jitter remains one of the most important design issues for successful operation of high speed serial links. This abstract introduces methods to model and estimate data dependent jitter (DDJ), in presence of capacitive and inductive discontinuities that result due to vias and right angular bends. The model shows that these discontinuities can have significant impact on DDJ, especially at high data rates. The proposed model is extensively verified with SPICE and show very good results.\",\"PeriodicalId\":313560,\"journal\":{\"name\":\"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEPS.2011.6100225\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS.2011.6100225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modeling of ISI in high speed serial I/Os terminated with discontinuities
Timing jitter remains one of the most important design issues for successful operation of high speed serial links. This abstract introduces methods to model and estimate data dependent jitter (DDJ), in presence of capacitive and inductive discontinuities that result due to vias and right angular bends. The model shows that these discontinuities can have significant impact on DDJ, especially at high data rates. The proposed model is extensively verified with SPICE and show very good results.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
