{"title":"基于环形vco的分采样锁相环CMOS电路，抖动0.73 ps，功耗20.4 mW","authors":"Kenta Sogo, A. Toya, T. Kikkawa","doi":"10.1109/ASPDAC.2013.6509576","DOIUrl":null,"url":null,"abstract":"This paper presents a ring voltage-controlledoscillator (ring-VCO)-based sub-sampling phase locked loop(PLL) CMOS circuit with low phase noise and low jitter. A 2.08 GHz PLL is developed by use of 65 nm CMOS technology. The in-band phase noise is -119.1 dBc/Hz at 1 MHz and the output jitter integrated from 1 kHz to 10 MHz is 0.73 ps (rms) with the power consumpition 20.4 mW. The normalized jitter-power product is -229.7 dB.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption\",\"authors\":\"Kenta Sogo, A. Toya, T. Kikkawa\",\"doi\":\"10.1109/ASPDAC.2013.6509576\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a ring voltage-controlledoscillator (ring-VCO)-based sub-sampling phase locked loop(PLL) CMOS circuit with low phase noise and low jitter. A 2.08 GHz PLL is developed by use of 65 nm CMOS technology. The in-band phase noise is -119.1 dBc/Hz at 1 MHz and the output jitter integrated from 1 kHz to 10 MHz is 0.73 ps (rms) with the power consumpition 20.4 mW. The normalized jitter-power product is -229.7 dB.\",\"PeriodicalId\":297528,\"journal\":{\"name\":\"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"volume\":\"2008 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.2013.6509576\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2013.6509576","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption
This paper presents a ring voltage-controlledoscillator (ring-VCO)-based sub-sampling phase locked loop(PLL) CMOS circuit with low phase noise and low jitter. A 2.08 GHz PLL is developed by use of 65 nm CMOS technology. The in-band phase noise is -119.1 dBc/Hz at 1 MHz and the output jitter integrated from 1 kHz to 10 MHz is 0.73 ps (rms) with the power consumpition 20.4 mW. The normalized jitter-power product is -229.7 dB.
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