完全耗尽SOI结构的限制

R. Lawrence, G. Campisi, G.J. Shontz, G. Pollack, R. Sundaresan
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引用次数: 1

摘要

作者展示了在不同外延硅厚度下,不同几何形状的完全耗尽晶体管的迁移率和阈值电压行为。采用电特性技术,在厚度为150 ~ 300 nm的外延硅上检测栅极几何形状在0.6 ~ 3 μ m之间的完全耗尽SIMOX SOI前置和后置晶体管。随着沟道长度的缩短和外延硅厚度的减小,n沟道迁移率和阈值电压下降。迁移率的下降归因于小几何形状的高电场。SOI优于散装,完全耗尽的SOI优于未完全耗尽的SOI。超薄SOI,与完全耗尽同义,使用窄栅极,因此将观察到迁移率下降的问题。完全耗尽的SOI减轻了但不能消除对迁移率的场依赖性。
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Limitations to fully-depleted SOI structures
The authors demonstrate the mobility and threshold voltage behavior for fully depleted transistors of various geometries on various epitaxial silicon thicknesses. Electrical characterization techniques were used to examine fully depleted SIMOX SOI front- and back-gate transistors of gate geometries between 0.6 and 3 mu m on epitaxial silicon of thicknesses between 150 and 300 nm. Degradation in N-channel mobilities and threshold voltages was observed for short channel lengths and decreasing epitaxial silicon thickness. The decrease in mobility was attributed to the higher electric fields for small geometries. SOI is better than bulk, and fully depleted SOI is better than non-fully depleted SOI. Ultra thin SOI, synonymous with fully depleted, uses narrow gates, and thus the problem of degradation in mobility will be observed. Fully depleted SOI mitigates but does not remove the field dependence of mobility.<>
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