Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145750
P.C. Karulkar, P.E. Belk
A new technique for determining the generation lifetime in fully-depleted, enhancement-mode SOI (silicon-on-insulator) MOSFETs is described. Island isolated, fully depleted n-channel MOSFETs of various widths and lengths fabricated in different thicknesses of SIMOX (separation by implantation of oxygen) SOI films were used in this experiment. The nature of the charge generation and the charge accumulation processes at the interface between the Si film and the SIMOX buried oxide is complicated and unknown. Hence it is difficult to model analytically the first transient. The problem can be simplified by studying the second, smaller transient which is observed when the back side of the Si film is further accumulated by increasing the negative substrate bias. Both the first and the second transient were studied as functions of the bias conditions and device geometry.<>
{"title":"Generation lifetime in fully depleted, enhancement mode SOI MOSFETs","authors":"P.C. Karulkar, P.E. Belk","doi":"10.1109/SOSSOI.1990.145750","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145750","url":null,"abstract":"A new technique for determining the generation lifetime in fully-depleted, enhancement-mode SOI (silicon-on-insulator) MOSFETs is described. Island isolated, fully depleted n-channel MOSFETs of various widths and lengths fabricated in different thicknesses of SIMOX (separation by implantation of oxygen) SOI films were used in this experiment. The nature of the charge generation and the charge accumulation processes at the interface between the Si film and the SIMOX buried oxide is complicated and unknown. Hence it is difficult to model analytically the first transient. The problem can be simplified by studying the second, smaller transient which is observed when the back side of the Si film is further accumulated by increasing the negative substrate bias. Both the first and the second transient were studied as functions of the bias conditions and device geometry.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"20 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120809228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145770
T. Huang, I. Wu, A. Lewis, A. Chiang, R. Bruce
Polysilicon low-voltage (LV) and high-voltage (HV) thin-film transistors (TFTs) required in high-performance large-area devices, such as printers and LCD displays, are considered. The authors (1990) proposed an improved HVTFT device structure with an independently-biased metal field plate (FP) overlapping the entire offset region. The new FP-HVTFT eliminates the expensive lightly-doped-drain implant required in the conventional offset-gate HVTFTs and the current-pinching effects commonly observed in conventional offset-gate polysilicon HVTFTs. The authors report the effects of offset length (L/sub off/) on the new FP-HVTFTs, as the device characteristics of the conventional offset-gate polysilicon HVTFTs are known to be very sensitive to L/sub off/, and L/sub off/ is set by the alignment between two masking layers in actual device fabrication. The feasibility is reported of using the field-plate device as a low-voltage TFT for reducing the off-state leakage current.<>
{"title":"Polysilicon thin film transistors with field-plate-induced drain junction for both high-voltage and low-voltage applications","authors":"T. Huang, I. Wu, A. Lewis, A. Chiang, R. Bruce","doi":"10.1109/SOSSOI.1990.145770","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145770","url":null,"abstract":"Polysilicon low-voltage (LV) and high-voltage (HV) thin-film transistors (TFTs) required in high-performance large-area devices, such as printers and LCD displays, are considered. The authors (1990) proposed an improved HVTFT device structure with an independently-biased metal field plate (FP) overlapping the entire offset region. The new FP-HVTFT eliminates the expensive lightly-doped-drain implant required in the conventional offset-gate HVTFTs and the current-pinching effects commonly observed in conventional offset-gate polysilicon HVTFTs. The authors report the effects of offset length (L/sub off/) on the new FP-HVTFTs, as the device characteristics of the conventional offset-gate polysilicon HVTFTs are known to be very sensitive to L/sub off/, and L/sub off/ is set by the alignment between two masking layers in actual device fabrication. The feasibility is reported of using the field-plate device as a low-voltage TFT for reducing the off-state leakage current.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114948761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145736
S. D. Russell, B. Offord, K. Weiner
Nanosecond thermal processing (NTP) using a XeCl excimer laser was employed in the fabrication of npn bipolar transistors in silicon-on-sapphire (SOS). Functional devices, with current gain approach 100, were obtained. The deleterious effects of diffusion pipes in SOS material were minimized using rapid laser activation of ion implanted dopant. Devices were fabricated using n-type epitaxially deposited silicon on double-solid-phase-epitaxy (DSPE) improved SOS. The total thickness of the first and second silicon epi-layers was nominally 2.0 mu m. Devices were fabricated using three different laser fluences for the emitter anneal. This corresponds to a variation in melt duration and corresponding metallurgical junction depth.<>
{"title":"Bipolar transistors in silicon-on-sapphire (SOS): effects of nanosecond thermal processing","authors":"S. D. Russell, B. Offord, K. Weiner","doi":"10.1109/SOSSOI.1990.145736","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145736","url":null,"abstract":"Nanosecond thermal processing (NTP) using a XeCl excimer laser was employed in the fabrication of npn bipolar transistors in silicon-on-sapphire (SOS). Functional devices, with current gain approach 100, were obtained. The deleterious effects of diffusion pipes in SOS material were minimized using rapid laser activation of ion implanted dopant. Devices were fabricated using n-type epitaxially deposited silicon on double-solid-phase-epitaxy (DSPE) improved SOS. The total thickness of the first and second silicon epi-layers was nominally 2.0 mu m. Devices were fabricated using three different laser fluences for the emitter anneal. This corresponds to a variation in melt duration and corresponding metallurgical junction depth.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132033270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145698
T. Ouisse, S. Cristoloveanu, G. Borel
Degradation of submicron MOSFETs by hot carrier injection is addressed. Results illustrating the sensitivity of the front and bank interfaces to various hot-carrier injection conditions are presented. The influence of gate, substrate, and drain biases, duration, and channel length is evaluated. The devices were LOCOS isolated, N-channel LDD, and conventional P-channel MOSFETs with 1- mu m length. The localization of interface defects near the drain was studied. It is found that, in general, front channel transistors are very tolerant to aging. Once the LDD spacer was optimized, the degradation subsequent to 150 h of stress was almost insignificant. No degradation of the back interface occurred after stressing the front channel. Results obtained by stressing the back channel transistor are discussed. The back channel transconductance behavior is described.<>
{"title":"Hot carrier-induced aging of short channel SIMOX devices","authors":"T. Ouisse, S. Cristoloveanu, G. Borel","doi":"10.1109/SOSSOI.1990.145698","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145698","url":null,"abstract":"Degradation of submicron MOSFETs by hot carrier injection is addressed. Results illustrating the sensitivity of the front and bank interfaces to various hot-carrier injection conditions are presented. The influence of gate, substrate, and drain biases, duration, and channel length is evaluated. The devices were LOCOS isolated, N-channel LDD, and conventional P-channel MOSFETs with 1- mu m length. The localization of interface defects near the drain was studied. It is found that, in general, front channel transistors are very tolerant to aging. Once the LDD spacer was optimized, the degradation subsequent to 150 h of stress was almost insignificant. No degradation of the back interface occurred after stressing the front channel. Results obtained by stressing the back channel transistor are discussed. The back channel transconductance behavior is described.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126487362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145700
D. Ioannou, X. Zhong, G. Campisi, H. Hughes
The interface characterization for very thin (fully depleted) SOI (silicon-on-insulator) layers is addressed. A new technique, dynamic transconductance, has recently been developed for bulk MOSFETs and exhibited important advantages. The technique has been successfully adapted to partially depleted and depletion mode SOI MOSFETs. A model for the application of the dynamic transconductance technique in fully depleted SOI MOSFETs is developed, and the experimental conditions are described. A demonstration of the validity of the model is given by applying the technique to study fully developed SIMOX (separation by implantation of oxygen) MOSFETs.<>
{"title":"Interface characterization in fully depleted SOI MOSFETs by dynamic transconductance","authors":"D. Ioannou, X. Zhong, G. Campisi, H. Hughes","doi":"10.1109/SOSSOI.1990.145700","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145700","url":null,"abstract":"The interface characterization for very thin (fully depleted) SOI (silicon-on-insulator) layers is addressed. A new technique, dynamic transconductance, has recently been developed for bulk MOSFETs and exhibited important advantages. The technique has been successfully adapted to partially depleted and depletion mode SOI MOSFETs. A model for the application of the dynamic transconductance technique in fully depleted SOI MOSFETs is developed, and the experimental conditions are described. A demonstration of the validity of the model is given by applying the technique to study fully developed SIMOX (separation by implantation of oxygen) MOSFETs.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127563703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145697
G. Reimbold, P. Saint Bonnet, B. Giffard, A. Auberton-Herve
Aging characteristics of 1.3- mu m silicon-on-insulator (SOI) CMOS transistors were studied for two different low doped drain (LDD) configurations. Fundamental differences concerning hot carrier effects were observed, and the impact on reliability was clarified. It appears that overall transistor performances are very sensitive to LDD optimization: low N-doping is recommended for low ionization rate, subsequent good blocking voltage, and intrinsic VG/sub bl/ increase during aging; high N-, in spite of small low time shifts, must be used carefully if initial blocking characteristics and bipolar effects are critical. In such cases, bulk transistor recommendations (high N- must be used in order to maintain high electric field under the transistor gate) may not be suitable for SOI transistors.<>
{"title":"Influence of LDD on aging of SOI NMOS transistors","authors":"G. Reimbold, P. Saint Bonnet, B. Giffard, A. Auberton-Herve","doi":"10.1109/SOSSOI.1990.145697","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145697","url":null,"abstract":"Aging characteristics of 1.3- mu m silicon-on-insulator (SOI) CMOS transistors were studied for two different low doped drain (LDD) configurations. Fundamental differences concerning hot carrier effects were observed, and the impact on reliability was clarified. It appears that overall transistor performances are very sensitive to LDD optimization: low N-doping is recommended for low ionization rate, subsequent good blocking voltage, and intrinsic VG/sub bl/ increase during aging; high N-, in spite of small low time shifts, must be used carefully if initial blocking characteristics and bipolar effects are critical. In such cases, bulk transistor recommendations (high N- must be used in order to maintain high electric field under the transistor gate) may not be suitable for SOI transistors.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133973347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145694
M. Gao, E. Simoen, C. Claeys, G. Declerck
The multistable V/sub T/ behavior of silicon-on-insulator (SOI) MOSFETs is considered. This phenomenon, the MCCM (multistable charge controlled memory) effect, was first found in non-fully depleted SOI n-MOSFET samples operating at 77 K when negative back gate bias V/sub G2/ was applied. When the applied V/sub G2/ was swept from zero-voltage towards a negative value, e.g. -40 V, the V/sub T/ of the front gate would shift higher with rather good linearity within a V/sub G2/ span of about 20-30 V. The increase in V/sub T/ can be up to 2-3 V. The MCCM effect is only related to the coupling between the front and the back gates and does not depend on whether there are junctions or a potential well in the body. All the transistors investigated operate in the non-fully depleted regime for both high and low states at both room and low temperatures. The measurement results show that such multi-stable V/sub T/ behavior also occurs in the N/sup +/N/sup -/N/sup +/ accumulation mode SOI n-MOSFETs.<>
{"title":"The multistable memory effect in accumulation mode SOI MOSFETs at low temperatures","authors":"M. Gao, E. Simoen, C. Claeys, G. Declerck","doi":"10.1109/SOSSOI.1990.145694","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145694","url":null,"abstract":"The multistable V/sub T/ behavior of silicon-on-insulator (SOI) MOSFETs is considered. This phenomenon, the MCCM (multistable charge controlled memory) effect, was first found in non-fully depleted SOI n-MOSFET samples operating at 77 K when negative back gate bias V/sub G2/ was applied. When the applied V/sub G2/ was swept from zero-voltage towards a negative value, e.g. -40 V, the V/sub T/ of the front gate would shift higher with rather good linearity within a V/sub G2/ span of about 20-30 V. The increase in V/sub T/ can be up to 2-3 V. The MCCM effect is only related to the coupling between the front and the back gates and does not depend on whether there are junctions or a potential well in the body. All the transistors investigated operate in the non-fully depleted regime for both high and low states at both room and low temperatures. The measurement results show that such multi-stable V/sub T/ behavior also occurs in the N/sup +/N/sup -/N/sup +/ accumulation mode SOI n-MOSFETs.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134391663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145708
D. L. Leung, J. Knudsen, D. Swanson, B. Hill, D. Mayer
The effect of process parameters on the quality of recrystallized material using rapid thermal processing (RTP) was evaluated. Both X-ray rocking curve and Read camera analysis were used to verify the crystalline quality of the regrown material. It is shown that RTP is a viable method for agglomerating the interfacial oxide at a silicon/polysilicon boundary before epitaxial growth. The material quality was observed to improve with increasing RTP time and temperature cycles. The optimum thermal anneal cycle was 600 degrees C for 18 h and 800 degrees C for 3 h. The improvement in the number of defects over the previously used ion implantation process is about two orders of magnitude.<>
{"title":"Native silicon oxide agglomeration prior to solid-phase epitaxy using rapid thermal processing","authors":"D. L. Leung, J. Knudsen, D. Swanson, B. Hill, D. Mayer","doi":"10.1109/SOSSOI.1990.145708","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145708","url":null,"abstract":"The effect of process parameters on the quality of recrystallized material using rapid thermal processing (RTP) was evaluated. Both X-ray rocking curve and Read camera analysis were used to verify the crystalline quality of the regrown material. It is shown that RTP is a viable method for agglomerating the interfacial oxide at a silicon/polysilicon boundary before epitaxial growth. The material quality was observed to improve with increasing RTP time and temperature cycles. The optimum thermal anneal cycle was 600 degrees C for 18 h and 800 degrees C for 3 h. The improvement in the number of defects over the previously used ion implantation process is about two orders of magnitude.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132509272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145739
P. Pronko, A. McCormick, W. Maszara
The use of keV ion implantation of boron for the bond and etch-back SOI (BESOI) technique is addressed. Ion implantation of boron at 2.5 MeV was used in order to place the boron peak and residual tail of the boron distribution deep enough, so that a region of the original silicon material with acceptably low boron concentration persists near the active-layer-SiO/sub 2/ interface. The objective was to determine whether improvements in final uniformity were possible using the MeV implants compared to the more conventional epi-layer technique. Results show that a final thickness of 0.3 mu m of single crystal silicon on insulator can be produced with thickness nonuniformity of 28 to 30 nm averaged over 9 points on a 2"*2" area. The final oxidation-stripping steps contributed to most of this nonuniformity. Additional difficulties arose as a result of the extensive oxidation stripping used in the terminal processing steps. Etch pit analysis of the final material revealed substantial oxidation induced stacking faults in the finished material ( approximately 300 cm/sup -2/, average length approximately 50 mu m).<>
{"title":"Epi-less bond etch SOI using MeV ion implantation","authors":"P. Pronko, A. McCormick, W. Maszara","doi":"10.1109/SOSSOI.1990.145739","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145739","url":null,"abstract":"The use of keV ion implantation of boron for the bond and etch-back SOI (BESOI) technique is addressed. Ion implantation of boron at 2.5 MeV was used in order to place the boron peak and residual tail of the boron distribution deep enough, so that a region of the original silicon material with acceptably low boron concentration persists near the active-layer-SiO/sub 2/ interface. The objective was to determine whether improvements in final uniformity were possible using the MeV implants compared to the more conventional epi-layer technique. Results show that a final thickness of 0.3 mu m of single crystal silicon on insulator can be produced with thickness nonuniformity of 28 to 30 nm averaged over 9 points on a 2\"*2\" area. The final oxidation-stripping steps contributed to most of this nonuniformity. Additional difficulties arose as a result of the extensive oxidation stripping used in the terminal processing steps. Etch pit analysis of the final material revealed substantial oxidation induced stacking faults in the finished material ( approximately 300 cm/sup -2/, average length approximately 50 mu m).<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145754
S. Takahashi, Y. Hayashi, S. Wada, T. Kunio
The device transfer method for obtaining SOI (silicon-on-insulator) devices with crystallinity similar to that of bulk silicon substrates. The structural feature of SOI devices obtained by the device transfer method is that the adhesive layer below the thin active device layer plays a role as an insulator. The authors describe the effect of mobile ions in the adhesive layer on the drain leakage current characteristics of the SOI devices. NMOSFET/SOI and PMOSFET/SOI with low leakage currents are obtained by the device transfer method using polyimide resin as an adhesive. Low Na/sup +/ content in the polyimide prevents back-channel formation in the SOI devices.<>
{"title":"Effects of adhesive properties on SOI devices obtained by device transfer method","authors":"S. Takahashi, Y. Hayashi, S. Wada, T. Kunio","doi":"10.1109/SOSSOI.1990.145754","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145754","url":null,"abstract":"The device transfer method for obtaining SOI (silicon-on-insulator) devices with crystallinity similar to that of bulk silicon substrates. The structural feature of SOI devices obtained by the device transfer method is that the adhesive layer below the thin active device layer plays a role as an insulator. The authors describe the effect of mobile ions in the adhesive layer on the drain leakage current characteristics of the SOI devices. NMOSFET/SOI and PMOSFET/SOI with low leakage currents are obtained by the device transfer method using polyimide resin as an adhesive. Low Na/sup +/ content in the polyimide prevents back-channel formation in the SOI devices.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"434 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116171750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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