Geometric compaction of building-block layout

A geometric approach for building-block layout compaction is presented. With a systematic method of automatic jog insertion, the authors have proved that the proposed algorithm achieves the lower bound of one-dimensional compaction with jog insertion. The approach presented is extremely powerful and provides a very efficient way to compact very complicated VLSI systems. When the input chip is given in symbolic form, the algorithm can be used to space the chip only if the chip can be expanded at every scan line. In this case, the maximum moves of some objects will be negative; the objects are actually moved up in the y -direction compaction to expand the space