将系统划分为asic

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186089

K. E. Dubowski

{"title":"将系统划分为asic","authors":"K. E. Dubowski","doi":"10.1109/ASIC.1990.186089","DOIUrl":null,"url":null,"abstract":"Partitioning considerations for systems that contain digital, analog, and memory components are discussed. Optimal partitioning requires consideration of the product features and performance, market size and share of that market, the product life cycle, system price, system cost, and manufacturing capability. The system specification should quantify each of these items. The system specification is a guide for partitioning the system. The optimal partitioning meets all system specifications at the lowest total system cost.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"107 Pt 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Partitioning systems into ASICs\",\"authors\":\"K. E. Dubowski\",\"doi\":\"10.1109/ASIC.1990.186089\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Partitioning considerations for systems that contain digital, analog, and memory components are discussed. Optimal partitioning requires consideration of the product features and performance, market size and share of that market, the product life cycle, system price, system cost, and manufacturing capability. The system specification should quantify each of these items. The system specification is a guide for partitioning the system. The optimal partitioning meets all system specifications at the lowest total system cost.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"107 Pt 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186089\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186089","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

讨论了包含数字、模拟和内存组件的系统的分区注意事项。最优划分需要考虑产品特性和性能、市场规模和市场份额、产品生命周期、系统价格、系统成本和制造能力。系统规范应该量化这些项目中的每一个。系统规范是对系统进行分区的指南。最优分区以最低的系统总成本满足所有系统规格。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Partitioning systems into ASICs

Partitioning considerations for systems that contain digital, analog, and memory components are discussed. Optimal partitioning requires consideration of the product features and performance, market size and share of that market, the product life cycle, system price, system cost, and manufacturing capability. The system specification should quantify each of these items. The system specification is a guide for partitioning the system. The optimal partitioning meets all system specifications at the lowest total system cost.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

自引率

0.00%

发文量

期刊最新文献

A development system for an SRAM-based user-reprogrammable gate array Automated CAE tools for full custom design of bipolar analog ASICs A 200 MHz 100 K ECL output buffer for CMOS ASICs Multi circular buffer controller chip for advanced ESM system Rapid prototyping, is there an educational dilemma? (ASIC design)