B. Vandevelde, A. Ivankovic, B. Debecker, M. Lofrano, K. Vanstreels, W. Guo, V. Cherman, M. Gonzalez, G. van der Plas, I. De Wolf, E. Beyne, Z. Tokei
{"title":"IC-Package交互","authors":"B. Vandevelde, A. Ivankovic, B. Debecker, M. Lofrano, K. Vanstreels, W. Guo, V. Cherman, M. Gonzalez, G. van der Plas, I. De Wolf, E. Beyne, Z. Tokei","doi":"10.1109/EUROSIME.2013.6529992","DOIUrl":null,"url":null,"abstract":"Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing k value. These so-called (ultra) low-k materials have a reduced stiffness and adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC's use thinned dies (down to 25μm) which can cause much higher stresses at transistor level, resulting in mobility shifts.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"IC-Package Interaction\",\"authors\":\"B. Vandevelde, A. Ivankovic, B. Debecker, M. Lofrano, K. Vanstreels, W. Guo, V. Cherman, M. Gonzalez, G. van der Plas, I. De Wolf, E. Beyne, Z. Tokei\",\"doi\":\"10.1109/EUROSIME.2013.6529992\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing k value. These so-called (ultra) low-k materials have a reduced stiffness and adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC's use thinned dies (down to 25μm) which can cause much higher stresses at transistor level, resulting in mobility shifts.\",\"PeriodicalId\":270532,\"journal\":{\"name\":\"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUROSIME.2013.6529992\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUROSIME.2013.6529992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing k value. These so-called (ultra) low-k materials have a reduced stiffness and adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC's use thinned dies (down to 25μm) which can cause much higher stresses at transistor level, resulting in mobility shifts.