Concurrent path sensitization in timing analysis

The authors describe a new two-step approach for determining the delay of the longest statically sensitizable path(s) in a combinational circuit. In the first step, the conditions for sensitizing all paths with the same path delay, D, are derived. In the second step, these conditions are checked for consistency by a Boolean satisfiability algorithm. This approach is unique in that it enumerates paths implicitly, giving it a decided performance edge over explicit path enumeration methods. The authors describe an implementation of this approach in an experimental timing analysis program, STA, and present preliminary results of its application to a representative set of benchmarks.<>