C. Ng, S. Ashtaputre, E. Chambers, Kieu-Huong Do, S.-T. Hui, R. Mody, D. Wong
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A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs
The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industry's most complex sea-of-gates gate arrays
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