Investigations studying the electromigration phenomena in interconnects

The main trends in consumer electronics are increasing product performances and costs reduction. These trends lead to an ongoing integration on package level which leads to a decreasing size of the solder contacts. This goes along with a higher sensibility to thermal-mechanical stress and the immanent void formation due to electromigration (EM) effects in interfaces and bulk materials like solder fillets or solder balls Following the Flip Chip-Technology in terms of Chip Size Packages or other miniaturized components, the size of solder bump interconnects have been significantly reduced with the development of high-density packaging, and therefore the evaluation of the electromigration behavior in solder bumps is significantly required. The paper proposes evaluation trials to test the electromigration resistance of different Pb-free solders, also with special additions to minimize material transport phenomena at interfaces and in the bulk (SnAgCu, SnAg+, SnBi+, SnAgBiSb+. SnAgBiIn+). Miniaturized interconnects with sufficient current density are under investigation to cause electromigration as phenomena concerning the diffusion of metallic atoms induced by high density electron flow and Joule heating, that can create local defects in terms of voids, etc. With the rapid downsizing of interconnections, the electromigration-resistant solder material and interfaces becomes more interest. In addition to that, for power electronic applications the acceptable current density must be compared with the design orientated constructional parameter in terms of back side metallizations of the die, bump or ball interconnects and the Cu width and thickness of wiring solutions in the package and the surrounding area. Results will be presented to discuss the risk of EM and solutions to stabilize interfaces. The electromigration effects are also under investigation for extended power electronics applications under the influence of Cu trace dimensions, electrical and thermal interfaces, current density applied, higher operating temperatures and metallizations in the vertical layer stack of power modules.