A 25mA CMOS LDO with −85dB PSRR at 2.5MHz

A CMOS low-dropout regulator (LDO) with high power-supply rejection ratio (PSRR) achieved by the proposed supply ripple feed-forward path is presented in this paper. The LDO is simple with two additional low-pass filters included. No extra power is consumed when comparing to the traditional design. The proposed LDO is implemented in 0.18-μ m CMOS technology. It occupies active area of 0.042 mm2. With the proposed embedded supply ripple feed-forward path, in the maximum loading of 25 mA, it achieves PSRR of -85 dB at 2.5 MHz and PSRR better than -55 dB when frequency is below 5 MHz with a 4.7-μF output capacitor. The measured quiescent current is 15 μA only. The overshoot and undershoot voltages are less than 40 mV when loading changes between 1 mA and 25 mA within 40 ns. The LDO achieves line and load regulations of 3 mV/V and 50 μV/mA, respectively.