高k/金属栅极三门SOI纳米线晶体管缩窄至10nm宽度

2012 13th International Conference on Ultimate Integration on Silicon (ULIS) Pub Date : 2012-03-06 DOI:10.1109/ULIS.2012.6193351

R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz, C. Comboroure, P. Perreau, E. Ernst, M. Samson, V. Maffini-Alvaro, C. Tabone, S. Barnola, D. Munteanu, G. Ghibaudo, S. Monfray, F. Boeuf, T. Poiroux

{"title":"高k/金属栅极三门SOI纳米线晶体管缩窄至10nm宽度","authors":"R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz, C. Comboroure, P. Perreau, E. Ernst, M. Samson, V. Maffini-Alvaro, C. Tabone, S. Barnola, D. Munteanu, G. Ghibaudo, S. Monfray, F. Boeuf, T. Poiroux","doi":"10.1109/ULIS.2012.6193351","DOIUrl":null,"url":null,"abstract":"In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"46","resultStr":"{\"title\":\"Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width\",\"authors\":\"R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz, C. Comboroure, P. Perreau, E. Ernst, M. Samson, V. Maffini-Alvaro, C. Tabone, S. Barnola, D. Munteanu, G. Ghibaudo, S. Monfray, F. Boeuf, T. Poiroux\",\"doi\":\"10.1109/ULIS.2012.6193351\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.\",\"PeriodicalId\":350544,\"journal\":{\"name\":\"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-03-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"46\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ULIS.2012.6193351\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ULIS.2012.6193351","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 46

摘要

本文研究了具有高k/金属栅极的三栅极纳米线(TGNW)场效应管，作为未来CMOS技术节点(14纳米及以上)平面器件的替代方法。介绍并讨论了硅膜厚度(H)和纳米线宽度(W)对长通道和短通道器件电性能的影响。我们发现TGNW中的输运性质完全由(100)顶表面和(110)侧壁的加性贡献决定。与宽平面器件相比，缩小TGNW场效应管的静电完整性(SS和DIBL)得到了明显的改善。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

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2012 13th International Conference on Ultimate Integration on Silicon (ULIS)

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