基于28nm CMOS的22.5 - 27.7 ghz快速锁相数字锁相环,用于毫米波通信,RMS抖动为220秒

Cheng-Hsueh Tsai, F. Pepe, G. Mangraviti, Zhiwei Zong, J. Craninckx, P. Wambacq
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引用次数: 2

摘要

我们提出了一种用于毫米波通信的22.5 - 27.7 ghz快速锁相低相位噪声的bang-bang数字锁相环。通过提出的换挡算法实现快速锁定,扩大锁相环带宽以更快地解决问题,并有序地减少锁相环带宽以提高抖动性能。基于变压器反馈和可调谐源桥电容的数字控制振荡器(DCO)在宽调谐范围内(FoM为- 184 dBc/Hz和fmt为- 191 dBc/Hz)具有低相位噪声(PN)。该锁相环的核心面积为0.09 mm2,功耗为25 mW, RMS为- 239 dB,抖动值为220-fs。通过我们的换挡算法,其沉降时间从780µs提高到45µs。对于60 ghz通信,其倍频系数为2.5,该锁相环覆盖了IEEE-802.11ad的所有六个通道频率,并能够支持128 QAM及更高频率。
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A 22.5–27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter
We present a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm, scaling up the PLL bandwidth for faster settling, and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO), based on transformer feedback with a tunable source-bridged capacitor, exhibits low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoMT of −191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW, giving FoMRMS of −239 dB. Its settling time improves from 780 to 45 µs with our gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.
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