采用双聚(n+/p+)栅极、Ti-salicide、双金属技术，适用于亚微米CMOS ASIC和逻辑应用

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56786

Shih-Wei Sun, M. Swenson, J. Yeargain, C. Lee, C. Swift, J. Pfiester, W. Bibeau, W. Atwell

{"title":"采用双聚(n+/p+)栅极、Ti-salicide、双金属技术，适用于亚微米CMOS ASIC和逻辑应用","authors":"Shih-Wei Sun, M. Swenson, J. Yeargain, C. Lee, C. Swift, J. Pfiester, W. Bibeau, W. Atwell","doi":"10.1109/CICC.1989.56786","DOIUrl":null,"url":null,"abstract":"The process architecture and device characteristics of a submicrometer CMOS n+/p+ poly gate, Ti-salicide, double-metal technology are described. Tradeoffs among circuit shrinkability, device gain, and hot-carrier-injection susceptibility are discussed. This technology has been successfully implemented in a 0.8-μm unified-design-rule high-performance high-end MPU product","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A dual-poly (n+/p+) gate, Ti-salicide, double-metal technology for submicron CMOS ASIC and logic applications\",\"authors\":\"Shih-Wei Sun, M. Swenson, J. Yeargain, C. Lee, C. Swift, J. Pfiester, W. Bibeau, W. Atwell\",\"doi\":\"10.1109/CICC.1989.56786\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The process architecture and device characteristics of a submicrometer CMOS n+/p+ poly gate, Ti-salicide, double-metal technology are described. Tradeoffs among circuit shrinkability, device gain, and hot-carrier-injection susceptibility are discussed. This technology has been successfully implemented in a 0.8-μm unified-design-rule high-performance high-end MPU product\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56786\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

介绍了一种亚微米CMOS n+/p+多栅极、Ti-salicide、双金属技术的工艺结构和器件特点。讨论了电路收缩性、器件增益和热载流子注入敏感性之间的权衡。该技术已成功应用于0.8 μm统一设计规则的高性能高端微处理器产品中

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A dual-poly (n+/p+) gate, Ti-salicide, double-metal technology for submicron CMOS ASIC and logic applications

The process architecture and device characteristics of a submicrometer CMOS n+/p+ poly gate, Ti-salicide, double-metal technology are described. Tradeoffs among circuit shrinkability, device gain, and hot-carrier-injection susceptibility are discussed. This technology has been successfully implemented in a 0.8-μm unified-design-rule high-performance high-end MPU product

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

自引率

0.00%

发文量

期刊最新文献

A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array A gate matrix deformation and three-dimensional maze routing for dense MOS module generation A submicron CMOS triple level metal technology for ASIC applications Hot carrier effects on CMOS circuit performance The QML-an approach for qualifying ASICs