Ultra-low power MOSFET and tunneling FET technologies using III-V and Ge

CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V/Ge channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to form these new materials on Si is a common key issue. The wafer bonding technologies are utilized for this purpose. We demonstrate the operation and the electrical characteristics of a variety of III-V/Ge MOSFETs and TFETs including the hetero-structures.