F. Longnos, M. Reyboz, N. Jovanovic, A. Levisse, T. Benoist, G. Suraci, O. Thomas, E. Vianello, G. Molas, B. De Salvo, L. Perniola
{"title":"CBRAM拐角分析稳健设计解决方案","authors":"F. Longnos, M. Reyboz, N. Jovanovic, A. Levisse, T. Benoist, G. Suraci, O. Thomas, E. Vianello, G. Molas, B. De Salvo, L. Perniola","doi":"10.1109/NVMTS.2014.7060850","DOIUrl":null,"url":null,"abstract":"In this paper, a comprehensive investigation of programming conditions in an oxide-based CBRAM device is presented. 1T-1R devices (both isolated and in a 8×8 matrix) are electrically characterized in a range of logic compatible programming conditions. Starting from the electrical results, programming conditions optimizing the memory window (ROFF/RON>25 in the worst case) and the resistance variability are identified. A corner approach is presented to fully calibrate a CBRAM compact model. The model has been implemented into an electrical simulator to assess performances of NVFF and memory circuit.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CBRAM corner analysis for robust design solutions\",\"authors\":\"F. Longnos, M. Reyboz, N. Jovanovic, A. Levisse, T. Benoist, G. Suraci, O. Thomas, E. Vianello, G. Molas, B. De Salvo, L. Perniola\",\"doi\":\"10.1109/NVMTS.2014.7060850\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a comprehensive investigation of programming conditions in an oxide-based CBRAM device is presented. 1T-1R devices (both isolated and in a 8×8 matrix) are electrically characterized in a range of logic compatible programming conditions. Starting from the electrical results, programming conditions optimizing the memory window (ROFF/RON>25 in the worst case) and the resistance variability are identified. A corner approach is presented to fully calibrate a CBRAM compact model. The model has been implemented into an electrical simulator to assess performances of NVFF and memory circuit.\",\"PeriodicalId\":275170,\"journal\":{\"name\":\"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NVMTS.2014.7060850\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMTS.2014.7060850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, a comprehensive investigation of programming conditions in an oxide-based CBRAM device is presented. 1T-1R devices (both isolated and in a 8×8 matrix) are electrically characterized in a range of logic compatible programming conditions. Starting from the electrical results, programming conditions optimizing the memory window (ROFF/RON>25 in the worst case) and the resistance variability are identified. A corner approach is presented to fully calibrate a CBRAM compact model. The model has been implemented into an electrical simulator to assess performances of NVFF and memory circuit.