M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra
{"title":"2mb嵌入式相变存储器,具有16ns读访问时间和5mb /s写吞吐量的90纳米BCD技术,用于汽车应用","authors":"M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra","doi":"10.1109/ESSCIRC.2019.8902656","DOIUrl":null,"url":null,"abstract":"This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications\",\"authors\":\"M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra\",\"doi\":\"10.1109/ESSCIRC.2019.8902656\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.\",\"PeriodicalId\":402948,\"journal\":{\"name\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2019.8902656\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902656","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications
This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.