一种自动化的，结构化的布局方法，用于交错焊盘，I/ o绑定ASIC设计

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186167

L.Y. Lu, M. D. Alston

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引用次数: 0

摘要

讨论了基于高引脚计数单元的BiCMOS ASIC设计的设计方法。描述了通过特定于工具的shell脚本、宏、文件重新格式化/转换软件和应用软件对不同供应商的CAD工具进行编排，以系统地放置和路由I/O垫单元、I/O电路单元和核心逻辑单元，快速完成错开垫、I/O绑定ASIC的正确构造布局

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An automated, structured layout methodology for staggered pad, I/O-bound ASIC design

A design methodology developed and implemented for high-pin-count cell-based BiCMOS ASIC designs is discussed. Described is the orchestration of different vendors' CAD tools via tool-specific shell scripts, macros, file reformatting/conversion software and application software to methodically place and route I/O pad cells, I/O circuit cells, and core logic megacells, rapidly completing the correct-by-construction layout of a staggered-pad, I/O-bound ASIC.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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