3D全局互连参数提取器全芯片全局关键路径分析

Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI:10.1109/EPEP.1997.634036

S. Oh, K. Okasaki, J. Moll, O. S. Nakagawa, N. Chang

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引用次数: 2

摘要

开发了一种三维全局互连参数提取器(GIPER)，为全芯片全局关键路径分析提供了实用的提取工具。与完整的3D数值模拟相比，它在HP 9000/755工作站上每网几分钟内提取典型全局互连的互连参数(R,C)，精度为5%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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3D Global Interconnect Parameter ExtractoR for full-chip global critical path analysis

A 3D Global Interconnect Parameter ExtractoR (GIPER) has been developed to provide a practical extraction tool for the full-chip global critical path analysis. It extracts the interconnect parameters (R,C) of a typical global interconnect within several minutes per net on a HP 9000/755 workstation within 5% accuracy compared to full 3D numerical simulations.

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Electrical Performance of Electronic Packaging

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