{"title":"先进Cu/CVD低k介电材料130nm工艺技术集成——失效分析与良率提升案例研究","authors":"C. Tsang, Y. Su, V.N. Bliznetsov, G.T. Ang","doi":"10.1109/IPFA.2003.1222740","DOIUrl":null,"url":null,"abstract":"We reported the failure analysis of 130 nm Cu/CVD low k film back-end-of-line (BEOL) process and successfully identified the root causes of failures leading to electrical yield loss of the process. We also demonstrated the significant yield enhancements through a) optimization of via & trench etch recipes and post-etch clean condition, b) tightened defectivity control and c) in-line monitoring control.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"130 nm process technology integration of advanced Cu/CVD low k dielectric material-case study of failure analysis and yield enhancement\",\"authors\":\"C. Tsang, Y. Su, V.N. Bliznetsov, G.T. Ang\",\"doi\":\"10.1109/IPFA.2003.1222740\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We reported the failure analysis of 130 nm Cu/CVD low k film back-end-of-line (BEOL) process and successfully identified the root causes of failures leading to electrical yield loss of the process. We also demonstrated the significant yield enhancements through a) optimization of via & trench etch recipes and post-etch clean condition, b) tightened defectivity control and c) in-line monitoring control.\",\"PeriodicalId\":266326,\"journal\":{\"name\":\"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-07-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2003.1222740\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2003.1222740","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
130 nm process technology integration of advanced Cu/CVD low k dielectric material-case study of failure analysis and yield enhancement
We reported the failure analysis of 130 nm Cu/CVD low k film back-end-of-line (BEOL) process and successfully identified the root causes of failures leading to electrical yield loss of the process. We also demonstrated the significant yield enhancements through a) optimization of via & trench etch recipes and post-etch clean condition, b) tightened defectivity control and c) in-line monitoring control.
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