超薄栅极电介质MOS结构中氧化物厚度提取的改进方法

ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307) Pub Date : 1999-03-15 DOI:10.1109/ICMTS.1999.766226

G. Ghibaudo, S. Bruyère, T. Devoivre, B. Desalvo, E. Vincent

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引用次数: 11

摘要

提出了一种适用于先进CMOS技术的评价氧化层厚度的改进方法。为此，适当地结合Maserjian的技术(Maserjian et al.， Solid State Electron。vol. 17, pp. 335-9, 1974)和Vincent的方法(Vincent等人，Proc. IEEE微电子测试结构vol. 10, pp. 105-10, 1997)被用来减轻提取过程中固有的未知参数，这取决于所使用的载波统计。该方法已成功应用于栅极氧化层厚度从7 nm到1.8 nm的各种工艺中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improved method for the oxide thickness extraction in MOS structures with ultra-thin gate dielectrics

An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique (Maserjian et al., Solid State Electron. vol. 17, pp. 335-9, 1974) and of Vincent's method (Vincent et al., Proc. IEEE Microelectronic Test Structures vol. 10, pp. 105-10, 1997) is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm down to 1.8 nm.

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ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)

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