使用德州仪器的Scope架构将IEEE 1149.1兼容的边界扫描逻辑设计到ASIC中

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186154

J. Koeter

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摘要

讨论了在Verilog中描述和模拟行为，并使用Synopsys进行综合和优化的设计。，在优化设计中加入IEEE 1149.1兼容(Scope)逻辑，并进行了Mentor门级仿真。考察了Scope逻辑对芯片的性能和面积的影响，并采用综合方法将其最小化

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Designing IEEE 1149.1 compatible boundary-scan logic into an ASIC using Texas Instrument's Scope architecture

A design that was described and simulated behaviorally in Verilog, and synthesized and optimized using Synopsys, is discussed., IEEE 1149.1-compatible (Scope) logic was added to the optimized design and Mentor gate-level simulations were performed. The performance and area impact on the chip of the Scope logic is examined and synthesis is used to minimize it.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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