{"title":"5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ调制器，带数字I/Q校准，用于GNSS接收机","authors":"Zehong Zhang, Yang Xu, Nan Qi, B. Chi","doi":"10.1109/ASSCC.2013.6691065","DOIUrl":null,"url":null,"abstract":"This paper presents a dual-mode 2nd-order, multi-bit reconfigurable continuous-time quadrature bandpass sigma-delta (CT QBP ΣΔ) modulator employing power scaling technique (PST) for low-IF GNSS receivers. The proposed modulator is capable of supporting both narrow band (NB) of 5MHz bandwidth (BW) and wideband (WB) of 20MHz BW with sampling frequencies of 160MHz and 480MHz, respectively. To solve the instability issue caused by the excess loop delay (ELD) in WB mode, an additional DAC is directly feedback to the input of a summing amplifier and the ELD is fixed to half of the sampling period. Digital I/Q calibration after the decimation is employed to improve the image-rejection ratio (IRR). Implemented in 65nm CMOS, the modulator achieves 65.9/53.7dB SNDR, 76.7/65.9dB SFDR and more than 60dB IRR after calibration across 5/20MHz BW with center frequencies of 4/12MHz. Powered by a 1.2-V supply, the modulator consumes 3.5/6.8mW, resulting in FOMs of 264/516fJ/conversion.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers\",\"authors\":\"Zehong Zhang, Yang Xu, Nan Qi, B. Chi\",\"doi\":\"10.1109/ASSCC.2013.6691065\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a dual-mode 2nd-order, multi-bit reconfigurable continuous-time quadrature bandpass sigma-delta (CT QBP ΣΔ) modulator employing power scaling technique (PST) for low-IF GNSS receivers. The proposed modulator is capable of supporting both narrow band (NB) of 5MHz bandwidth (BW) and wideband (WB) of 20MHz BW with sampling frequencies of 160MHz and 480MHz, respectively. To solve the instability issue caused by the excess loop delay (ELD) in WB mode, an additional DAC is directly feedback to the input of a summing amplifier and the ELD is fixed to half of the sampling period. Digital I/Q calibration after the decimation is employed to improve the image-rejection ratio (IRR). Implemented in 65nm CMOS, the modulator achieves 65.9/53.7dB SNDR, 76.7/65.9dB SFDR and more than 60dB IRR after calibration across 5/20MHz BW with center frequencies of 4/12MHz. Powered by a 1.2-V supply, the modulator consumes 3.5/6.8mW, resulting in FOMs of 264/516fJ/conversion.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6691065\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers
This paper presents a dual-mode 2nd-order, multi-bit reconfigurable continuous-time quadrature bandpass sigma-delta (CT QBP ΣΔ) modulator employing power scaling technique (PST) for low-IF GNSS receivers. The proposed modulator is capable of supporting both narrow band (NB) of 5MHz bandwidth (BW) and wideband (WB) of 20MHz BW with sampling frequencies of 160MHz and 480MHz, respectively. To solve the instability issue caused by the excess loop delay (ELD) in WB mode, an additional DAC is directly feedback to the input of a summing amplifier and the ELD is fixed to half of the sampling period. Digital I/Q calibration after the decimation is employed to improve the image-rejection ratio (IRR). Implemented in 65nm CMOS, the modulator achieves 65.9/53.7dB SNDR, 76.7/65.9dB SFDR and more than 60dB IRR after calibration across 5/20MHz BW with center frequencies of 4/12MHz. Powered by a 1.2-V supply, the modulator consumes 3.5/6.8mW, resulting in FOMs of 264/516fJ/conversion.
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