基于90nm CMOS技术的15-20GHz延时锁相环

Jung-Yu Chang, Chi-Nan Chuang, Shen-Iuan Liu
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引用次数: 1

摘要

利用90 nm CMOS技术制备了15 GHz~20 GHz的延时锁相环(DLL)。它不仅放宽了对压控延迟线(VCDL)的速度要求,而且允许VCDL不在最高频率下工作。当DLL工作在20 GHz时,测量到的均方根抖动和峰对峰抖动分别为0.813 ps和6.62 ps。核心面积为0.25 × 0.4 mm2, 0.9 V供电时功耗为49 mW。
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A 15–20GHz delay-locked loop in 90nm CMOS technology
A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.
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