用局部SIMOX技术制备介电袋绝缘体MOSFET自对准漏源

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI:10.1109/SOI.2005.1563550

Zhichao Lv, Hao Zhang, Jian Wang, L. Tian, Zhijian Li, Jiayin Sun, Jing Chen, Xi Wang

{"title":"用局部SIMOX技术制备介电袋绝缘体MOSFET自对准漏源","authors":"Zhichao Lv, Hao Zhang, Jian Wang, L. Tian, Zhijian Li, Jiayin Sun, Jing Chen, Xi Wang","doi":"10.1109/SOI.2005.1563550","DOIUrl":null,"url":null,"abstract":"In this work, a method to fabricate SA-DSOI MOSFET with dielectric pocket has been presented. Dielectric pocket and BOX are realized by local SIMOX technology. This novel structure results in good SCE and SHE suppression and higher speed performance, which is very important in nanoscale device design. With this novel self-aligned process, DSOI MOSFET can be scaled down to nano-scale and becomes a promising device.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Fabrication of self-aligned drain and source on insulator MOSFET with dielectric pocket by local SIMOX technology\",\"authors\":\"Zhichao Lv, Hao Zhang, Jian Wang, L. Tian, Zhijian Li, Jiayin Sun, Jing Chen, Xi Wang\",\"doi\":\"10.1109/SOI.2005.1563550\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a method to fabricate SA-DSOI MOSFET with dielectric pocket has been presented. Dielectric pocket and BOX are realized by local SIMOX technology. This novel structure results in good SCE and SHE suppression and higher speed performance, which is very important in nanoscale device design. With this novel self-aligned process, DSOI MOSFET can be scaled down to nano-scale and becomes a promising device.\",\"PeriodicalId\":116606,\"journal\":{\"name\":\"2005 IEEE International SOI Conference Proceedings\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2005.1563550\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563550","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

本文提出了一种带介电袋的SA-DSOI MOSFET的制备方法。介质袋和盒子采用本地SIMOX技术实现。这种新型结构具有良好的SCE和SHE抑制性能以及更高的速度性能，在纳米器件设计中具有重要意义。利用这种新颖的自对准工艺，DSOI MOSFET可以缩小到纳米级，成为一种很有前途的器件。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fabrication of self-aligned drain and source on insulator MOSFET with dielectric pocket by local SIMOX technology

In this work, a method to fabricate SA-DSOI MOSFET with dielectric pocket has been presented. Dielectric pocket and BOX are realized by local SIMOX technology. This novel structure results in good SCE and SHE suppression and higher speed performance, which is very important in nanoscale device design. With this novel self-aligned process, DSOI MOSFET can be scaled down to nano-scale and becomes a promising device.

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2005 IEEE International SOI Conference Proceedings

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