A.J.-H. Lee, J. A. Sabnis, M. Saniski, G. P. Sampson
{"title":"一个400mhz CMOS数据包收发芯片","authors":"A.J.-H. Lee, J. A. Sabnis, M. Saniski, G. P. Sampson","doi":"10.1109/CICC.1989.56772","DOIUrl":null,"url":null,"abstract":"The authors describe a very-high-performance CMOS device designed to transmit and receive packetized data. During the transmitting operations, bytewide data are converted to a single serial bit stream that can be transmitted on an optical fiber. In the receiving operations, the serial bit stream is converted into byte format with appropriate frame detection. Operations with bit rate at 400 Mb/s have been demonstrated. The on-chip pseudo-ECL input and output buffers provide high-speed, low-power interfaces","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 400 MHz CMOS packet transmitter-receiver chip\",\"authors\":\"A.J.-H. Lee, J. A. Sabnis, M. Saniski, G. P. Sampson\",\"doi\":\"10.1109/CICC.1989.56772\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe a very-high-performance CMOS device designed to transmit and receive packetized data. During the transmitting operations, bytewide data are converted to a single serial bit stream that can be transmitted on an optical fiber. In the receiving operations, the serial bit stream is converted into byte format with appropriate frame detection. Operations with bit rate at 400 Mb/s have been demonstrated. The on-chip pseudo-ECL input and output buffers provide high-speed, low-power interfaces\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56772\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors describe a very-high-performance CMOS device designed to transmit and receive packetized data. During the transmitting operations, bytewide data are converted to a single serial bit stream that can be transmitted on an optical fiber. In the receiving operations, the serial bit stream is converted into byte format with appropriate frame detection. Operations with bit rate at 400 Mb/s have been demonstrated. The on-chip pseudo-ECL input and output buffers provide high-speed, low-power interfaces
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