Myeungsu Kim, Kwengmook Lee, Yong-Il Kwon, Joonhyung Lim, T. Park
{"title":"带有自动校准环路的5ghz频率合成器","authors":"Myeungsu Kim, Kwengmook Lee, Yong-Il Kwon, Joonhyung Lim, T. Park","doi":"10.1109/RFIC.2007.380982","DOIUrl":null,"url":null,"abstract":"A 5-GHz frequency synthesizer for ZIGBEE(IEEE 802.15.4) was implemented. It consumes 13.5 mW adopting CMOS Logic divider and robust VCO from process and temperature variation by body voltage control of current source. It incorporates an automatic capacitor-bank tuning loop to extend frequency tuning range. This synthesizer was fabricated in 0.18-um technology; it consumes 7.5 mA at 1.8 V and offers 100 kHz-loop bandwidth and always -103 dBc/Hz at an offset of 1 MHz. the lock time is 30 us. The PLL output tuning range is 14% from 2.258 GHz to 2.614 GHz.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"5-GHz Frequency Synthesizer With Auto-Calibration Loop\",\"authors\":\"Myeungsu Kim, Kwengmook Lee, Yong-Il Kwon, Joonhyung Lim, T. Park\",\"doi\":\"10.1109/RFIC.2007.380982\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 5-GHz frequency synthesizer for ZIGBEE(IEEE 802.15.4) was implemented. It consumes 13.5 mW adopting CMOS Logic divider and robust VCO from process and temperature variation by body voltage control of current source. It incorporates an automatic capacitor-bank tuning loop to extend frequency tuning range. This synthesizer was fabricated in 0.18-um technology; it consumes 7.5 mA at 1.8 V and offers 100 kHz-loop bandwidth and always -103 dBc/Hz at an offset of 1 MHz. the lock time is 30 us. The PLL output tuning range is 14% from 2.258 GHz to 2.614 GHz.\",\"PeriodicalId\":356468,\"journal\":{\"name\":\"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2007.380982\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2007.380982","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
5-GHz Frequency Synthesizer With Auto-Calibration Loop
A 5-GHz frequency synthesizer for ZIGBEE(IEEE 802.15.4) was implemented. It consumes 13.5 mW adopting CMOS Logic divider and robust VCO from process and temperature variation by body voltage control of current source. It incorporates an automatic capacitor-bank tuning loop to extend frequency tuning range. This synthesizer was fabricated in 0.18-um technology; it consumes 7.5 mA at 1.8 V and offers 100 kHz-loop bandwidth and always -103 dBc/Hz at an offset of 1 MHz. the lock time is 30 us. The PLL output tuning range is 14% from 2.258 GHz to 2.614 GHz.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
