A 4ns 16k BiCMOS SRAM

A 2k x 8bit, ECL lOOK compatible BiCMOS SRAM with 4 ne 1 6 0 ' . -4.5V) address a c c e s s time is re6ort;d. The properly controlled bit . line voltageswing (60mV), a current sensing method and optimized ECL decoding circuits provide the reliable and fasf readout opeiation. The SRAM features an on chip write pulse generator. latches for input and output bits and a full six transistor CMOS cell array. Power dissipation is 1.9511 end chio size is 3.9x5.9mm2. The SRAM is curkently processed in 1.2um BiCMOS, using double metal, triple polysilicon end self aligned bipolar transistors. this contribution to saturation can be everted. The address access time is mainly determined by the wordline and bitline capacitence which deDends on the cell array-configuration. With respect to the driving capability of the Totem Pole buffer controlline wordline the best arrangement was fouGd to be 64 rows and 2 5 6 columns. B e a h l w r i t P a n d s m s p r i r . is shown in fig. 2 . The bitline ( Z B L l R ) potential is mainly fixed by two emitter followers (11T! 1ZT). Additionally a 30um PMOS transistor (12P) clamps the voltage swing to 60 mV. This small valtage swing is amplified by B bipolar sense ampiifier which consists oftwo stages. The first stage (15T, 14T). a bioolar differential pair, detects the voitage drop caused by the cell current at the resistors RSENSLl and RSENSR1. The voltage drop of the buried layer which connects the double collector contacts (11T, 12T) adds to the voltage drao at each sense resistor. 32 of these dif?erential pairs have common collectors and a common current source (16T). TO reduce voltage swing of the common collector nodes they are connected to the second stage. a.cascode configuration. which controlls the output buffer with latch. Column select is done a ECL signal of 200 mV voltage swing 1; the base of transistor 13T which works a s an emitter follower. If select signal is high, the current of the =ommon sense amplifier current source (16T) flows through the corresponding differential pair. For WRITE operation. clamp transistor (12P) and bipolar pullup transistors (11T. 12T) are switched off. while two NMOS transistors (12N. 13N); which connect bitline to the write bus. are switched on. The write bus 1BLLW. BLRW) itself is controlled by two.large NMOS transistors. An ECL WRITE pulse can be generated by an on chip C ~ n e r a t ~ r 1 W P G l . An external WRITE pulse signal can alternatively be used. An ECL multiplexer selects one of the both WRITE pulses. The WRITE bus consists of 16 signal lines end is controlled by 16 pull down NMOS transistors (200um). These are driven by 2x8 complementary CMOS signals which a r e generated from 8 DATA-IN signela. A system of 14 bias drivers supplies the 16k BiCMOS SRAM with the necessary reference voltaees. The SRAM features three operatio: modes: asynchronous without WPG or clock driven. with or without WPG. The clock input signal is internally converted to differential logic. Low output impedance emitter followers drive the two~separate clocknets to limit the load. The contribution of the different parts of the 16k BiCMOS SRAM to a c c e s 8 time and power dissipation are shown in table