M. Minami, N. Ohki, H. Ishida, T. Yamanaka, K. Ishibashi, A. Shimizu, T. Kure, T. Nishida, T. Nagano
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A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits
A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell area and a high-performance 1.8-V circuit are thus realized.
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