Warpage and RDL Stress Analysis in Large Fan-Out Package with Multi-Chiplet Integration

As the advanced packaging technology is required to fulfill digitalized industry with big data, such as high performance computing (HPC), data center server, router, and switcher applications. Due to the hunger from above market needs, great interests were induced by both research institutes and industry. Multiple chiplets integration can provide design flexibility, high performance and power efficiency. Therefore, advanced package technology is needed for this application. Chip-last FOCoS, one of the best options, is developed as advanced packaging technology to enable different functional chiplets within a single package. This technology can improve yield, performance and cost to shorten the time to market. The package warpage control is very challenging in assembly of larger fan-out package with multi-chip integration. The redistribution layer (RDL) trace broken risk is also key issue to influence package reliability in thermal cycling test (TCT). High CTE-mismatch effect was significantly occurred at die to die (D2D) gap. The RDL trace stress is more sensitive to material properties, process flow and geometric structure due to complex multi-layer structure in several materials. It is a tougher job to minimize RDL trace stress under each process limitation. In this paper, the RDL trace stress is compared in detail to trace layout, line/spaces (L/S), D2D gap distance and trace location at room temperature (RT) and high temperature (HT). The results indicate that the trace layout design and trace location play critical roles to enhance reliability performance.