面向移动和高性能计算应用的系统集成芯片(SoIC)的下一代设计和技术协同优化(DTCO)

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI:10.1109/IEDM13553.2020.9372005

Y. Cheng, F. Lee, M.F. Chen, J. Yuan, Tze-Chiang Huang, K.-J. Chen, C. Wang, C.-L. Chen, C. Tsai, Douglas C. H. Yu

{"title":"面向移动和高性能计算应用的系统集成芯片(SoIC)的下一代设计和技术协同优化(DTCO)","authors":"Y. Cheng, F. Lee, M.F. Chen, J. Yuan, Tze-Chiang Huang, K.-J. Chen, C. Wang, C.-L. Chen, C. Tsai, Douglas C. H. Yu","doi":"10.1109/IEDM13553.2020.9372005","DOIUrl":null,"url":null,"abstract":"This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications\",\"authors\":\"Y. Cheng, F. Lee, M.F. Chen, J. Yuan, Tze-Chiang Huang, K.-J. Chen, C. Wang, C.-L. Chen, C. Tsai, Douglas C. H. Yu\",\"doi\":\"10.1109/IEDM13553.2020.9372005\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.\",\"PeriodicalId\":415186,\"journal\":{\"name\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM13553.2020.9372005\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM13553.2020.9372005","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

本文展示了用于移动和高性能计算应用的系统集成芯片(SoIC)的下一代设计和技术协同优化(DTCO)，其中SoIC技术被提出将具有不同功能和技术的多芯片集成到单个SoC芯片中。新的DTCO包括整体芯片划分、芯片集成和互连。这些方法可用于缩短上市时间，并在性能和成本之间进行权衡。本文演示了两种堆叠CPU和内存芯片的原型，性能提高了15%，平均点对点距离减少了30%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications

This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.

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2020 IEEE International Electron Devices Meeting (IEDM)

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