{"title":"源极/漏极超低功耗模拟/RF UTBB mosfet","authors":"A. Kranti, J. Raskin, G. A. Armstrong","doi":"10.1109/ULIS.2011.5757997","DOIUrl":null,"url":null,"abstract":"We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (g<inf>m</inf>/I<inf>ds</inf>) and cut-off frequency (f<inf>T</inf>) product i.e. g<inf>m</inf>f<inf>T</inf>/I<inf>ds</inf> as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve g<inf>m</inf>f<inf>T</inf>/I<inf>ds</inf>, intrinsic voltage gain (A<inf>VO</inf>), cut-off frequency (f<inf>T</inf>) and linearity (VIP<inf>3</inf>) with downscaling.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Source/drain engineered ultra low power analog/RF UTBB MOSFETs\",\"authors\":\"A. Kranti, J. Raskin, G. A. Armstrong\",\"doi\":\"10.1109/ULIS.2011.5757997\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (g<inf>m</inf>/I<inf>ds</inf>) and cut-off frequency (f<inf>T</inf>) product i.e. g<inf>m</inf>f<inf>T</inf>/I<inf>ds</inf> as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve g<inf>m</inf>f<inf>T</inf>/I<inf>ds</inf>, intrinsic voltage gain (A<inf>VO</inf>), cut-off frequency (f<inf>T</inf>) and linearity (VIP<inf>3</inf>) with downscaling.\",\"PeriodicalId\":146779,\"journal\":{\"name\":\"Ulis 2011 Ultimate Integration on Silicon\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Ulis 2011 Ultimate Integration on Silicon\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ULIS.2011.5757997\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Ulis 2011 Ultimate Integration on Silicon","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ULIS.2011.5757997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Source/drain engineered ultra low power analog/RF UTBB MOSFETs
We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (gm/Ids) and cut-off frequency (fT) product i.e. gmfT/Ids as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve gmfT/Ids, intrinsic voltage gain (AVO), cut-off frequency (fT) and linearity (VIP3) with downscaling.
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