一种Intel 18253 ASIC芯片设计

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186189

Y.-I. Hsieh

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引用次数: 0

摘要

讨论了在ASIC CAD环境中为ASIC设计创建可执行和可综合(和/或可测试)规范的工程规则的建立。选择Intel 8253可编程定时器/计数器作为测试实例来说明该CAD技术的优缺点。对高性能基于单元的ASIC/IC CAD系统的需求对于该应用至关重要。

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An Intel 18253 ASIC chip design

The establishment of the engineering rules to create the executable and synthesizable (and/or testable) specification for an ASIC design in an ASIC CAD environment is discussed. The Intel 8253 programmable timer/counter was selected as a test example to illustrate the strengths and weaknesses of this CAD technology. The need for a high-performance cell-based ASIC/IC CAD system is critical for this application.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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