M. Steigerwalt, David Urrabazo, R. Baiocco, Ryan Kelly, A. Minns, Derek Dechamplain, Qifang Qiao, R. van Roijen
{"title":"氧化Rie工艺引起的线边缘粗糙度:主题:AM","authors":"M. Steigerwalt, David Urrabazo, R. Baiocco, Ryan Kelly, A. Minns, Derek Dechamplain, Qifang Qiao, R. van Roijen","doi":"10.1109/ASMC.2019.8791835","DOIUrl":null,"url":null,"abstract":"The performance of a subset of the logic devices on a recent new design showed unexpected variation. Analysis showed that the nitride/oxide spacer exhibited excessive roughness in certain areas of a logic chip, causing the observed device shift. To execute the experiments required to correct the issue we developed a method to use inline measurement to quantify spacer quality. This helped to improve spacer quality without delaying availability of the product.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Line Edge Roughness due to Oxide Rie Process : Topic: AM\",\"authors\":\"M. Steigerwalt, David Urrabazo, R. Baiocco, Ryan Kelly, A. Minns, Derek Dechamplain, Qifang Qiao, R. van Roijen\",\"doi\":\"10.1109/ASMC.2019.8791835\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The performance of a subset of the logic devices on a recent new design showed unexpected variation. Analysis showed that the nitride/oxide spacer exhibited excessive roughness in certain areas of a logic chip, causing the observed device shift. To execute the experiments required to correct the issue we developed a method to use inline measurement to quantify spacer quality. This helped to improve spacer quality without delaying availability of the product.\",\"PeriodicalId\":287541,\"journal\":{\"name\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2019.8791835\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2019.8791835","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Line Edge Roughness due to Oxide Rie Process : Topic: AM
The performance of a subset of the logic devices on a recent new design showed unexpected variation. Analysis showed that the nitride/oxide spacer exhibited excessive roughness in certain areas of a logic chip, causing the observed device shift. To execute the experiments required to correct the issue we developed a method to use inline measurement to quantify spacer quality. This helped to improve spacer quality without delaying availability of the product.
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