I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn
{"title":"早期可测试的可寻址逻辑(ETAL)测试结构:展示了在技术开发中使用替代逻辑生成学习测试结构","authors":"I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn","doi":"10.1109/ASMC.2019.8791769","DOIUrl":null,"url":null,"abstract":"Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the \"Early Testable Addressable Logic (ETAL)\" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development\",\"authors\":\"I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn\",\"doi\":\"10.1109/ASMC.2019.8791769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the \\\"Early Testable Addressable Logic (ETAL)\\\" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.\",\"PeriodicalId\":287541,\"journal\":{\"name\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2019.8791769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2019.8791769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development
Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the "Early Testable Addressable Logic (ETAL)" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.