W. Gootzen, M. Bellersen, L. D. Bruin, G. Rao, G. Rutten, D.L.W. Yen
{"title":"利用PETEOS与其他PECVD膜相结合的新型亚微米CMOS sram钝化工艺的评价","authors":"W. Gootzen, M. Bellersen, L. D. Bruin, G. Rao, G. Rutten, D.L.W. Yen","doi":"10.1109/VMIC.1989.77995","DOIUrl":null,"url":null,"abstract":"The final passivation layer affects the electrical behavior of a device and also influences various failure mechanisms in device, package, and product reliability by its interaction with the metal layers underneath and the packaging material above it. In order to address the various issues involved, several passivation schemes have been evaluated. A scheme using PECVD-TEOS in combination with other PECVD films for the 0.7- mu m and 0.5- mu m CMOS SRAM processes is proposed.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"216 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Evaluation of a novel passivation process for submicron CMOS SRAMs using PETEOS in combination with other PECVD films\",\"authors\":\"W. Gootzen, M. Bellersen, L. D. Bruin, G. Rao, G. Rutten, D.L.W. Yen\",\"doi\":\"10.1109/VMIC.1989.77995\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The final passivation layer affects the electrical behavior of a device and also influences various failure mechanisms in device, package, and product reliability by its interaction with the metal layers underneath and the packaging material above it. In order to address the various issues involved, several passivation schemes have been evaluated. A scheme using PECVD-TEOS in combination with other PECVD films for the 0.7- mu m and 0.5- mu m CMOS SRAM processes is proposed.<<ETX>>\",\"PeriodicalId\":302853,\"journal\":{\"name\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"volume\":\"216 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VMIC.1989.77995\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.77995","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
最终钝化层影响器件的电气行为，也影响器件、封装和产品可靠性中的各种失效机制，因为它与下面的金属层和上面的封装材料相互作用。为了解决所涉及的各种问题，对几种钝化方案进行了评价。提出了一种将PECVD- teos与其他PECVD膜结合用于0.7 μ m和0.5 μ m CMOS SRAM工艺的方案。
Evaluation of a novel passivation process for submicron CMOS SRAMs using PETEOS in combination with other PECVD films
The final passivation layer affects the electrical behavior of a device and also influences various failure mechanisms in device, package, and product reliability by its interaction with the metal layers underneath and the packaging material above it. In order to address the various issues involved, several passivation schemes have been evaluated. A scheme using PECVD-TEOS in combination with other PECVD films for the 0.7- mu m and 0.5- mu m CMOS SRAM processes is proposed.<>
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
