Early stage chip/package/board co-design techniques for system-on-chip

With the advancements in semiconductor process technologies in recent years, many circuits are mounted on small dies and the number of interface pins has rapidly increased. The demand for smaller chip/package sizes has come about in order to reduce costs. This paper describes the early stage chip/package/board co-design techniques which reduce chip and package size by cutting down the number of PDN (Power Distribution Network) pads/balls and improve the routability of the package. The key techniques are early stage package/board properties estimation and IR drop estimation. These techniques have a good degree of accuracy even at early stage estimation and a short processing time. From experimental result using a 45-nm process TEG (Test Element Group) chip, the package size was reduced by 21.5%, and the chip size was reduced by 16.4% in comparison with the original design which was designed conventional techniques. The experimental result demonstrates the validation of the proposed techniques.