IEEE标准VHDL 1076的形式化语义研究

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410687

S. Olcoz, J. Colom

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引用次数: 31

摘要

解决了对VHDL的正式解释的需要。用于此目的的正式模型是彩色Petri网，因为它们可以覆盖VHDL的所有方面。作者从基于通信过程的VHDL底层可执行模型入手。VHDL描述的形式化模型来自于用户定义进程、内核进程(VHDL模拟器)以及它们之间的通信链接的Petri网规范。这种方法也可以应用于具有相同底层范式的其他hdl

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Toward a formal semantics of IEEE Std. VHDL 1076

The need for a formal interpretation of VHDL is addressed. The formal model used for this purpose is colored Petri nets because they can cover all aspects of VHDL. The authors start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process (VHDL simulator), and the communicating links between them. This approach can also be applied to other HDLs with the same underlying paradigm.<>

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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