{"title":"一种新的路径临界计算方法","authors":"Róbert Tamási, M. Siebert, E. Gramatová, P. Fiser","doi":"10.1109/DDECS.2016.7482478","DOIUrl":null,"url":null,"abstract":"Technology scaling and manufacturing process affect the performance of digital circuits, making them more vulnerable to environmental influences. Some defects are manifested as delay faults. Some various factors have impact to signal propagation delay. A new method is presented for determining factors impact measurement on the path delay in the digital circuits. The method is focused to find the best weights of the factors used as parameters for the PaCGen (Parameterized Critical Path Generator) system. PaCGen is used for critical paths selection based on static timing analysis data with impact of factors to propagation delay. Experimental results are provided using the ISCAS'89 benchmark circuits.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new method for path criticality calculation\",\"authors\":\"Róbert Tamási, M. Siebert, E. Gramatová, P. Fiser\",\"doi\":\"10.1109/DDECS.2016.7482478\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Technology scaling and manufacturing process affect the performance of digital circuits, making them more vulnerable to environmental influences. Some defects are manifested as delay faults. Some various factors have impact to signal propagation delay. A new method is presented for determining factors impact measurement on the path delay in the digital circuits. The method is focused to find the best weights of the factors used as parameters for the PaCGen (Parameterized Critical Path Generator) system. PaCGen is used for critical paths selection based on static timing analysis data with impact of factors to propagation delay. Experimental results are provided using the ISCAS'89 benchmark circuits.\",\"PeriodicalId\":404733,\"journal\":{\"name\":\"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2016.7482478\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2016.7482478","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Technology scaling and manufacturing process affect the performance of digital circuits, making them more vulnerable to environmental influences. Some defects are manifested as delay faults. Some various factors have impact to signal propagation delay. A new method is presented for determining factors impact measurement on the path delay in the digital circuits. The method is focused to find the best weights of the factors used as parameters for the PaCGen (Parameterized Critical Path Generator) system. PaCGen is used for critical paths selection based on static timing analysis data with impact of factors to propagation delay. Experimental results are provided using the ISCAS'89 benchmark circuits.