{"title":"亚波长/sup TM/设计的硅级物理验证","authors":"F. Chang, Melissa Kwok, K. Rachlin, R. Pack","doi":"10.1109/ICVD.1999.745221","DOIUrl":null,"url":null,"abstract":"In this paper, we show that the use of SubWavelength mask design for improved IC performance and yield presents new challenges for traditional deep submicron ECAD physical verification tools. We demonstrate the need for new approaches and propose two tools for the silicon-level physical verification of SubWavelength designs. Fortunately, these tools work within current physical verification design flows.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Silicon-level physical verification of SubWavelength/sup TM/ designs\",\"authors\":\"F. Chang, Melissa Kwok, K. Rachlin, R. Pack\",\"doi\":\"10.1109/ICVD.1999.745221\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we show that the use of SubWavelength mask design for improved IC performance and yield presents new challenges for traditional deep submicron ECAD physical verification tools. We demonstrate the need for new approaches and propose two tools for the silicon-level physical verification of SubWavelength designs. Fortunately, these tools work within current physical verification design flows.\",\"PeriodicalId\":443373,\"journal\":{\"name\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1999.745221\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745221","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Silicon-level physical verification of SubWavelength/sup TM/ designs
In this paper, we show that the use of SubWavelength mask design for improved IC performance and yield presents new challenges for traditional deep submicron ECAD physical verification tools. We demonstrate the need for new approaches and propose two tools for the silicon-level physical verification of SubWavelength designs. Fortunately, these tools work within current physical verification design flows.
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